A conventional AC to DC power converter typically includes a boost converter front end for power factor correction of the input bulk voltage generated from the AC input power source and a downstream DC to DC converter to convert the unregulated bulk voltage into an output voltage that satisfies the voltage regulation and transient response requirements of the power converter. In most applications, there is a “Power Hold-up” requirement for such converters. In other words, the DC output voltage generated by the downstream DC to DC converter is expected to stay in regulation for a predefined amount of time after the input power source has failed. When the input power source fails, a bulk capacitor in the power converter typically provides the necessary temporary power for the downstream DC to DC converter as it discharges. In most AC to DC converters, the minimum hold-up time is required to be the time necessary to maintain voltage regulation for at least one missing AC cycle of the input AC power source. Thus, this hold-up time is typically at least 16 mS for a 60 Hz line frequency AC power source and 20 mS for a 50 Hz line frequency AC power source.
FIG. 1 shows a prior art AC to DC power converter 10 that includes a bulk capacitor C1 for providing the desired hold-up time. The rectified input AC voltage is boosted by a power factor correcting boost converter, comprising an inductor L1, a switch SW1, a diode D1, and a bulk capacitor C1. This boosted bulk voltage across bulk capacitor C1 is input to the DC to DC converter. When the input AC voltage fails, the bulk capacitor C1 starts to discharge and the voltage across it starts to fall. The DC to DC converter responds to this falling voltage by expanding its duty cycle in order to maintain output voltage regulation. At a certain voltage, the duty cycle reaches its maximum limit and output voltage regulation is no longer maintained. This lowest operating voltage point determines how much energy in the bulk capacitor C1 can be utilized for hold-up.
Some power supply topologies, such as a flyback power converter, can operate up to a very wide duty cycle, with certain penalties on performance. Other topologies, such as the forward converter, cannot operate over a very wide duty cycle since, for very wide duty cycle variations, the efficiency drops significantly due to high peak currents. This significant drop in efficiency limits the practical input voltage tolerance of the DC to DC converter. As a result, for forward converters and other topologies that cannot operate over a very wide duty cycle, only a limited amount of energy stored in the bulk capacitor C1 is utilized during a power failure mode. For example, most DC to DC converters operate in the range of 100% of the normal bulk voltage level down to 75% if this level. Thus, for higher power, it is necessary to increase the size of the bulk capacitor to meet the hold-up requirement. This results in inefficient use of the available space in the power supply, affecting the power density.
As an example, a typical power factor corrected, 3 KW power supply receiving input power from a standard AC outlet and configured as in FIG. 1 will include a hard-switched power factor corrected boost converter front end and a zero voltage switching (ZVS) full bridge converter for the downstream DC to DC converter. A typical value for a bulk capacitor C1 is 2350 uF and is comprised of 5 electrolytic capacitors of 470 uF each. Typical efficiencies of 88% are obtained for such converters.
In modern AC to DC and DC to DC power supplies, the requirement of higher power density is increasing day by day. Higher power converter switching frequencies reduce the sizes of the magnetic components significantly. Improvement in efficiency is also obtained by using better and faster semiconductor devices and more efficient topologies, which enables the size of the associated heat sinks to be reduced. However, the size of the bulk capacitor still remains the same, and this severely restricts advancements in higher power density. A circuit is therefore needed that will enable use of most of the energy stored in the bulk capacitance, to thereby reduce bulk capacitor requirements while also improving the efficiency of the converter.
FIG. 2 shows another prior art AC to DC power converter 20 having three stages of power conversion, including a second stage buck converter between a front-end boost converter and a downstream DC to DC converter. The second stage buck converter comprises a switch SW2, a diode D3, an inductor L2, and a capacitor C2. The buck converter operates to step down the bulk voltage on the bulk capacitor C1 to a much lower value. Thus, the buck converter provides the downstream DC to DC converter with a well-regulated input voltage across capacitor C2. Upon failure of the line input AC voltage, bulk capacitor C1 starts to discharge, but the voltage across capacitor C2 is kept constant due to the wider regulation range of the second stage buck converter. For example, if the voltage across capacitor C2 is regulated to 0.5 Vb, where Vb is the nominal bulk voltage across C1, the energy utilization during the hold-up time is improved considerably. Consequently, either a smaller bulk capacitor can be used or the hold-up time increased if the same sized bulk capacitor is used.
A drawback of power converter 20 in FIG. 2 is that the additional buck converter operates continuously and dissipates power. As a result, for power converter 20, the improved efficiency of the downstream DC to DC converter due to the narrow input voltage range is more than offset by the additional dissipation in the buck converter.
For example, a typical power factor corrected, 3 KW power supply receiving input power from a standard AC outlet and using the topology shown in FIG. 2 would typically need a bulk capacitor C1 of 470 uF×3, a capacitor C2 of 470 uF, for a total capacitance of C1+C2=1880 uF. Typical efficiencies of 87.5% are obtained with such converters. Moreover, as the buck converter must operate at a duty cycle close to 50%, e.g. bucking the voltage from 400V to 200V, in order to enable a reduced bulk capacitor to be used, a large value is required for inductor L2 and capacitor C2.
FIG. 3 shows another prior art AC to DC power converter 30 that includes a bulk capacitor C2 for providing the desired hold-up time. Power converter 30 includes a power factor correction (PFC) boost front end converter having an inductor L1, a switch SW1, a diode D1, and a bulk capacitor C1. Power converter 30 generates a boosted bulk voltage across a capacitor C1, and at the same time, charges an energy storage capacitor C2 through a diode D2. As seen in FIG. 3, a second boost converter, identified as an auxiliary boost converter, includes an inductor L2, a switch SW2, and a diode D4 as boosting elements. The control loop of the second boost converter is set at a much lower voltage regulation point than that of first boost converter stage. Typically, this voltage regulation point is set at a level that is marginally higher than the regulation break voltage point of a conventional DC to DC converter. For example, if the nominal bulk voltage is Vb and the regulation break voltage point of the conventional DC to DC converter is 0.75Vb, the voltage regulation point of the second boost converter is set at around 0.8Vb. As a result, in normal operation, the second boost converter stage is always off and does not generate any power dissipation. Upon failure of the AC input, bulk capacitor C1 in power converter 30 continues to discharge while providing hold-up power to the DC to DC converter. When the voltage across bulk capacitor C1 falls to 0.8Vb in this example, the second boost converter starts to regulate using the energy from storage capacitor C2. Since this second boost converter stage can operate up to a very wide duty cycle, it can regulate the voltage across bulk capacitor C1 until most of the energy in storage capacitor C2 is utilized. Thus, power converter 30 provides an extended hold-up time while reducing the bulk capacitor size. Power converter 30 does, however, have several drawbacks as are illustrated with reference to FIGS. 3 and 4.
FIG. 4 is a timing diagram for power converter 30 in FIG. 3 that illustrates the operation of converter 30 in more detail, where Vb is shown as Vbulk. As seen in FIG. 3, power converter 30 requires two sets of capacitors, bulk capacitor C1 for normal operation filtering and hold-up and capacitor C2 for energy storage during an extended hold-up period. Despite the inclusion of a diode D3 between capacitor C1 and capacitor C2 in power converter 30, in normal operation capacitor C1 and capacitor C2 do not share the power handling equally. During normal operation, since capacitors C1 and C2 are both charged to an equal voltage level, diode D3 adds an extra voltage drop in the path of capacitor C2, and thus power converter 30 functions less efficiently. During hold-up, capacitor C2 will operate with capacitor C1 well, since the rate of discharge of capacitor C1 is high and capacitor C2 effectively becomes parallel to capacitor C1 when it is discharging. As a result, for power converter 30, capacitor C1 still must be sized to handle most of the ripple current of the first boost converter stage. The ripple is typically twice the line frequency, i.e., 100 Hz for a 50 Hz AC source line frequency and 120 Hz for a 60 Hz AC source. The ripple current rating and operating life parameters for the converter set the minimum possible size of capacitor C1 in power converter 30.
Another drawback of power converter 30 is that it requires an extra storage capacitor C2 which must be large enough to store enough energy to provide the required additional hold-up time. Still another drawback of power converter 30 is that it does not reduce the operational range of the DC to DC converter less than for other prior art converters. As a result, power converter 30 does not provide any performance gain over prior art converters.
For example, a typical power factor corrected, 3 KW power supply receiving input power from a standard AC outlet and configured as shown in FIG. 3 would typically need a bulk capacitor C1 of 470 uF×3, a capacitor C2 of 470 uF, resulting in a total capacitance of C1+C2=1880 uF. Typical efficiencies of 88% are attained with such converters. Thus, the efficiency of power converter 30 is not improved over that for the power converters in FIGS. 1 and 2 since the operating range of the DC to DC converter shown in FIG. 3 is not changed.
FIG. 5 shows a circuit diagram for a prior art AC-DC power converter 40 that provides line harmonic correction. Power converter 40 comprises a power factor corrected flyback converter that switches directly on the rectified AC input pulses. AC input power is applied at two input terminals and is conventionally used to produce unsmoothed DC through the use of a conventional bridge rectifier having two output terminals. A capacitor C1 is connected in series with a diode D2 across the terminals of the bridge rectifier. Power converter 100 includes a transformer T1 having a primary winding, a secondary winding, and an auxiliary winding, each having a first and a second end. In power converter 40, the auxiliary winding provides the energy for recharging the capacitor C1 during each flyback cycle of the flyback converter 40. The primary winding of transformer T1 in FIG. 5 is conventionally switched on and off at a predetermined frequency by means of a first switch SW1. The control signal input to switch SW1 is typically a conventional pulse width modulation (PWM) or power factor correction (PFC) type drive signal (details not shown). The secondary winding of transformer T1 is connected to a rectifying and filter circuit comprising a diode D3 and a capacitor C2, to produce the rated DC output voltage.
The charging of capacitor C1 in power converter 40 to a predetermined voltage is controlled by the circuit comprising the auxiliary winding, and a resistor R1 connected in series with a second switch SW2 and a diode D1 between one end of the auxiliary winding and one terminal of capacitor C1. The other terminal of capacitor C1 is connected to the second end of the auxiliary winding.
In operation, when switch SW1 of converter 40 closes, current flows in the primary of the transformer T1 and energy is stored therein. When the switch SW1 is opened, during the flyback period of converter 40, the polarity on the transformer T1 windings changes and the secondary rectifier diode D3 becomes forward biased. Diode D3 delivers power to a load as connected at the output terminals and stores energy in output capacitor C2. During this flyback period when switch SW1 is open, switch SW2 is turned on and capacitor C1 is charged to a predetermined voltage determined by the turns ratio between the primary winding and the auxiliary winding.
Thus, switch SW2 turns on only during the flyback period of converter 40. The voltage on capacitor C1 is usually selected low (around 50V or so). In normal operation, when the instantaneous voltage of the rectified AC pulse is higher than the voltage at which capacitor C1 is charged, diode D2 is reverse biased. Capacitor C1 will continue to hold its charge during this time. When this instantaneous voltage falls below the capacitor C1 voltage near the “valley point” of the rectified AC pulse, diode D2 becomes forward biased. As a result, capacitor C1 provides energy to transformer T1 to continue operation during this time. Capacitor C1 thus provides hold-up time during this period. Switch SW2 can also be held off when the charge on capacitor C1 is being used by converter 40 in order to reduce the peak currents in the transformer T1.
One drawback of the circuit in FIG. 5 is that capacitor C1 fails to provide the larger hold-up time required in most applications. If capacitor C1 is to provide a large hold-up time, then a large capacitor will be needed, since the voltage charge on capacitor C1 is very close to the voltage that exists at the bottom of the rectified pulse. As a result, there is poor energy utilization in this example.
The circuit in FIG. 5 can be improved using an extra boost conversion stage as taught in FIG. 1 in such a way that it extends the hold-up time of the converter 40, while reducing the bulk capacitor size. The additional stage would also improve the efficiency of the downstream DC to DC converter, while reducing the size of its output filter components. However, such a circuit would still have the drawbacks described above with respect to converter 10.
A circuit is therefore needed that will enable use of most of the energy stored in the bulk capacitor to thereby reduce bulk capacitor size requirements, while also improving efficiency.